/ 
Verilog-VCD-Writer-0.001
River stage zero No dependents
/ Verilog::VCD::Writer::Signal

NAME

Verilog::VCD::Writer::Signal - Signal abstraction layer for Verilog::VCD::Writer

VERSION

version 0.001

SYNOPSIS

use Verilog::VCD::Writer;
use Verilog::VCD::Writer::Signal;

# my $signal=Verilog::VCD::Signal(
# name=>'signalName',
# type=> 'wire'
# bitmax=>7,
# bitmin=>0)

DESCRIPTION

This module is designed to be called from the Verilog::VCD::Writer::Module module.

INTERFACE

DEPENDENCIES

SEE ALSO

AUTHOR

Vijayvithal Jahagirdar<jvs@cpan.org>

COPYRIGHT AND LICENSE

This software is copyright (c) 2017 by Vijayvithal.

This is free software; you can redistribute it and/or modify it under the same terms as the Perl 5 programming language system itself.