NAME

VerilogGrammar - Parsing HUGE gate level verilog files a little bit at a time.

SYNOPSIS

use VerilogGrammar;
my $parser = VerilogGrammar->new('filename.v');
$parser->design_items;

DESCRIPTION

This module defines a grammar for parsing simple gate-level verilog netlists. It uses Parse::Nibbler so that large files can be parsed in the program. The parser accumulates information on a module by module basis as it parses the file. To do something with this information, create a new package which overloads the design_items method and do something with each module as it is parsed.

This module is intended to be an example module that uses Parse::Nibbler.

EXPORT

None.

AUTHOR

# Copyright (c) 2001 Greg London. All rights reserved. # This program is free software; you can redistribute it and/or # modify it under the same terms as Perl itself.

contact the author via http://www.greglondon.com

SEE ALSO

Parse::Nibbler