NAME

Hardware::Vhdl::Parser - Perl extension for parsing VHDL code

SYNOPSIS

use Hardware::Vhdl::Parser;
$parser = new Hardware::Vhdl::Parser;

my @file = <>;
my $file = join('',@file);
$parser->design_file($file);

DESCRIPTION

################################################################## # Copyright (C) 2000 Greg London All Rights Reserved. # This program is free software; you can redistribute it and/or # modify it under the same terms as Perl itself. ##################################################################

This module defines the complete grammar needed to parse any VHDL code. By overloading this grammar, it is possible to easily create perl scripts which run through VHDL code and perform specific functions.

For example, a Hierarchy.pm uses Hardware::Vhdl::Parser to overload the grammar rule for component instantiations. This single modification will print out all instance names that occur in the module being parsed. This might be useful for creating an automatic build script, or a graphical hierarchical browser of a VHDL design.

AUTHOR

Greg London greg42@bellatlantic.net

SEE ALSO

perl(1). Parse::RecDescent