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Hardware-Verilog-Parser-0.12
River stage zero No dependents

Changes for version 0.12

  • minor patch. readme file incorrectly referred to non-existent verilog.pl file. parser.pl script now also report performance information for benchmarking. average is about 20 lines of verilog a second.

Modules

Hardware::Verilog::Parser
A complete grammar for parsing Verilog code using perl

Provides

Hardware::Verilog::Hierarchy
in Hierarchy.pm
Hardware::Verilog::StdLogic
in StdLogic.pm

Other files