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Hardware-Verilog-Parser-0.03
River stage zero No dependents
/ Hardware::Verilog::Parser

NAME

Hardware::Verilog::Parser - A complete grammar for parsing Verilog code using perl

SYNOPSIS

use Hardware::Verilog::Parser;
$parser = new Hardware::Verilog::Parser;

$parser->Filename(@ARGV);

DESCRIPTION

This module defines the complete grammar needed to parse any Verilog code. By overloading this grammar, it is possible to easily create perl scripts which run through Verilog code and perform specific functions.

This module is currently in PRE-RELEASE state, and subject to change without notice. Once the grammar is ironed out, I hope to declare it relatively stable.

AUTHOR

Greg London greg42@bellatlantic.net

Copyright (C) 2000 Greg London All Rights Reserved.

This program is free software; you can redistribute it and/or modify it under the same terms as Perl itself.

SEE ALSO

Parse::RecDescent

perl(1).