NAME

Verilog::VCD::Writer::Symbol - Signal name to symbol mapper. Private class nothing to see here.

VERSION

version 0.004

SYNOPSIS

use Verilog::VCD::Writer::Symbol;

This is a Singleton class to map the signal name to a compact symbol

AUTHOR

Vijayvithal Jahagirdar<jvs@cpan.org>

COPYRIGHT AND LICENSE

This software is copyright (c) 2017 by Vijayvithal.

This is free software; you can redistribute it and/or modify it under the same terms as the Perl 5 programming language system itself.